Side channels are an old problem on CPU’s. Can we solve them once and for all? We protect our secure code by mapping it in non-cacheable memory; and so by bypassing side channel-sensitive buffers (data and code caches, branch predictor buffers, etc.) on CPU’s, even disabling SMT, making concurrent access to caches pointless, and concurrent access to certain micro-architectural buffers impossible. In this talk we present an exploitable side channel that remains in DRAM when bypassing buffers and caches on the CPU and present realistic key recovery results.