Progress in Standardizing Cryptography Extensions for RISC-V Processors
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Presented at RSAC 2024 by
This panel will discuss the state of standardized cryptographic instruction set extensions for RISC-V processors. Lightweight instructions for scalar CPUs, high-performance instructions for vector CPUs, an entropy source interface, and “constant time” guarantees have been ratified. On-going work is in post-quantum cryptography and facilitating improved resistance to implementation attacks.