File:20140309 gmc vhdl fpga softcores.pdf // slides FPGAs can combine logic gates based on a description of a logical circuit written in a HDL. VHDL is one such language. While this may sound abstract, with soft-cores FPGA's become flexible microcontrollers. The internet hosts a number of GPL or BSD licensed IP-cores to make it easy to kickstart developing your own microprocessor. This talk introduces the basic concepts (FPGA's and a cursory view of VHDL) and describes how you can customize an off-the-shelf IP core with custom hardware circuits such as encryption engines, multimedia input and output and specialized I/O. Among available free cores are the well-known microprocessors 6502, 8088, 6800, ARM, 68000, 8085. This talk will present a very simple microprocessor core: the ZPU. The ZPU is a 32-bit stack-based microprocessor and is a great starting point if you are interested in experimenting with the inner workings of the microprocessor. It comes with a gcc toolchain to compile c into zpu object files. The talk will also point out freely available tools to get started with VHDL, including simulation and loading a design into an FPGA. One such tool will hopefully be demonstrated, showing a complete trace of all internal signals in the ZPU microprocessor while it is executing a hello world program written in c. With projects such as opencores, the principles of free software can be applied to hardware as well. Many of the opencores projects are wishbone compliant. Wishbone is a bus specified to promote interoperability between free IP-cores. Wishbone can be used to link I/O-controllers to the microprocessor, but it can also be used as a memory interface. The talk will introduce the wishbone bus and it's various read/write cycles. Wishbone promotes reuse of modules.